Icarus Verilog is a compiler implementation for the Verilog hardware description language with support for a substantial subset of SystemVerilog.
Its normal workflow preprocesses, parses and elaborates a design before generating code for a back-end target, most commonly the VVP simulation runtime. Although simulation is its principal use, the compiler is also useful for checking HDL source because it performs language parsing, elaboration and selectable warning diagnostics before code generation. Its long-established command-line workflow makes it suitable for scripting, automated testing and integration with other electronic design automation tools on Linux.
This is free and open source software.
Key Features
- Compiles hardware descriptions written using multiple generations of the Verilog language standard.
- Provides support for many SystemVerilog language constructs alongside traditional Verilog.
- Separates compilation from the VVP runtime used to execute the resulting simulation program.
- Offers a null code-generation target for syntax and compilation checking without producing simulation output.
- Provides selectable warning classes for identifying potentially problematic HDL constructs.
- Supports command files for projects where passing large collections of sources and options directly is inconvenient.
- Includes a preprocessor for macros, include files and other Verilog preprocessing facilities.
- Can generate several alternative output forms through its configurable target architecture.
- Supports VPI, allowing compiled C modules to interact with running Verilog simulations.
- Provides utilities to simplify building and linking VPI modules on supported systems.
- Supports waveform-generation workflows that can be inspected with compatible waveform viewers.
- Can participate in automated HDL testing environments as a compiler and simulation backend.
Website: github.com/steveicarus/iverilog
Support:
Developer: Stephen Williams and contributors
License: GNU General Public License v2.0
Icarus Verilog is written in C and C++. Learn C with our recommended free books and free tutorials. Learn C++ with our recommended free books and free tutorials.
Related Software
| Verilog Linter Tools | |
|---|---|
| Verilator | Fast SystemVerilog simulator with static code checks and diagnostics |
| Verible | SystemVerilog parser, formatter and language server |
| ICARUS Verilog | Verilog compiler and simulation system with broad language support |
| slang | SystemVerilog compiler and language services with detailed diagnostics |
| svlint | Configurable SystemVerilog source checker with flexible rule settings |
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