Verilog is a hardware description language used to model electronic systems, particularly digital circuits. SystemVerilog extends Verilog with a much larger set of features for hardware design and verification.
Checking HDL source before simulation or synthesis can save considerable time. Problems such as questionable constructs, width mismatches, unused signals, incomplete assignments, unintended implicit behaviour and violations of project coding rules are much easier to deal with early in the development cycle.
Verilog and SystemVerilog checking tools vary considerably in scope. Some concentrate on configurable coding and style rules. Others use a full compiler frontend, parsing and elaborating the design so they can identify problems which require a deeper understanding of the source. Formatting, language-server support, simulation and other development facilities may also be available.
These tools are useful to FPGA and ASIC developers writing RTL, verification engineers working with SystemVerilog test environments, and teams maintaining large hardware projects. They are also particularly well suited to automated development workflows, where source can be checked whenever code is committed or submitted for review. Students and hobbyists can benefit too, as diagnostics can expose mistakes before a design reaches simulation.
This article picks our favourite Verilog and SystemVerilog linting tools.
Here’s our verdict captured in a legendary LinuxLinks-style ratings chart. Only free and open source software is eligible for inclusion here.
Click the links in the table below to learn more about each tool.
| Verilog Linter Tools | |
|---|---|
| Verilator | Fast SystemVerilog simulator with static code checks and diagnostics |
| Verible | SystemVerilog parser, formatter and language server |
| ICARUS Verilog | Verilog compiler and simulation system with broad language support |
| slang | SystemVerilog compiler and language services with detailed diagnostics |
| svlint | Configurable SystemVerilog source checker with flexible rule settings |
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