svlint is a command-line linter for SystemVerilog source code.
It is built on the sv-parser parsing library and is designed around a configurable collection of rules rather than a fixed coding policy. Projects can enable the checks they need, use supplied rulesets aimed at different development scenarios, or maintain their own configuration in the source tree. This makes svlint useful for both straightforward syntax and style checking and more specialised hardware-development policies covering design and verification code. It can also participate in editor workflows through the related svls language server.
This is free and open source software.
Key Features
- Parses SystemVerilog source using the sv-parser infrastructure.
- Provides a broad collection of individual lint rules that can be switched on or off independently.
- Uses TOML configuration so lint policy can be stored alongside the source being checked.
- Searches parent directories for project configuration, allowing a single policy to cover an entire source tree.
- Includes predefined rulesets for syntax checking, general style, simulation and synthesis concerns.
- Provides separate supplied rulesets targeting design intent and verification intent.
- Can process individual source files as well as file lists used by larger SystemVerilog projects.
- Includes wrapper scripts for applying predefined configurations without manually specifying each rule.
- Can be incorporated into GitHub-based continuous integration through a companion action.
- Works with svls to expose related SystemVerilog tooling through editors supporting the Language Server Protocol.
- Provides detailed documentation of available checks and their configurable behaviour.
- Runs as a native command-line application suitable for automated hardware-development workflows on Linux.
Website: github.com/dalance/svlint
Support:
Developer: dalance
License: MIT License
svlint is written in Rust. Learn Rust with our recommended free books and free tutorials.
Related Software
| Verilog Linter Tools | |
|---|---|
| Verilator | Fast SystemVerilog simulator with static code checks and diagnostics |
| Verible | SystemVerilog parser, formatter and language server |
| ICARUS Verilog | Verilog compiler and simulation system with broad language support |
| slang | SystemVerilog compiler and language services with detailed diagnostics |
| svlint | Configurable SystemVerilog source checker with flexible rule settings |
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