slang is a fast SystemVerilog compiler and analysis tool offering parsing, elaboration, linting, diagnostics, AST access and Python bindings.
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Tag: electronic design automation
Icarus Verilog – Verilog compiler and simulation system
Icarus Verilog is a compiler implementation for the Verilog hardware description language
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Verilator – SystemVerilog simulator and lint system
Verilator is a SystemVerilog simulator and lint system aimed at high-performance digital design verification.
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svlint – configurable SystemVerilog linter
svlint is a configurable SystemVerilog linter with selectable rules, bundled rulesets, TOML configuration and editor integration through svls.
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Verible – SystemVerilog parser, linter, formatter and language server
Verible is a suite of SystemVerilog developer tools providing style linting, formatting, parsing, project analysis and language server support.
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